[parisc-linux] sched-O1-2.4.17-I3.patch, need help

[James Bottomley]

> >         while (1) {
> >                 void (*idle)(void) = pm_idle;
> >                 if (!idle)
> >                         idle = default_idle;
> > -               while (!current->need_resched)
> > +               if (!current->need_resched)
> >                         idle();
> >                 schedule();
> >                 check_pgt_cache();
>
> Dunno.

This is sending the idle thread back through the scheduler at least once every 
clock tick.  On the x86, idle() halts the processor until it receives an 
interrupt.

I *think* the reason is the idle tick rebalances the run queue but doesn't 
schedule the first task for execution (if there is one), so the call to 
schedule() does that.

However, there are more changes than just this (I just did the changes for a 
different arch).  You need to change p->processor to p->cpu in the SMP code.  
There may be other struct task changes that bite, but that looks like the only 
one in parisc.

You also get bitten (in I3) by the physical to logical CPU mapping problems.  
These are gone in J0, but now you have to introduce and extra migrate_process 
cross processor interrupt.

Probably the best way to work on this is to start a 2.5 parisc tree...

Good luck.

James Bottomley