[parisc-linux] 715 useful (fwd)

[Bill Katz (William)]

From: Alex deVries <adevries@thepuffingroup.com>
|On Sat, 13 Nov 1999, Matthew Wilcox wrote:
|> For the machines which have ASP, am I right in saying they have no other
|> sources of interrupts?  ie what I want to do is:
|
|I'm interpretting this question as:
|
|"For machines which have ASP, am I right in saying that no other IO
|devices apart from ASP generate interrupts to the CPU?"
|
|I think the answer to that question is no, because:
|- they have GSC slots, so you could have a card mode lasi or dino device
|- doesn't WAX have it's own interrupts?

Remember, ASP only exists on boxes that use the VSC/SGC I/O bus, i.e.
boxes that are pre-GSC.  Pre-GSC boxes will never have GSC slots,
or WAX, or Zalon.

The only expansion slots these boxes have are EISA, and EISA interrupts
come through ASP.

I learned a little more about these boxes friday.  The memory controller
in early 715s (/33, /50, /75) is called spider.  SPider actually 
sends the bus transaction to the processor to interrupt it.  It 
can interrupt the processor for any of its own reasons (memory
error, bus timeout, etc.)  It has one external interrupt pin, and
that is hooked to ASP.  I also did a quick scan through the docs
for the viper meomry controller used in 720/730/750, and it has one
external interrupt pin, so I think the assumption that all I/O 
interrupts come through ASP is valid.

Unfortunately spider was designed by the ex-Apollo floks in CHelmsford,
who basiclaly all left the company when R&D was consolidated in
Ft. COllins.  SO I have no good sources for an ERS for the spider chip.

	-Bill Katz