[parisc-linux] Proposal for altering our Page Table layouts

[Grant Grundler]

On Fri, Apr 09, 2004 at 08:38:04AM -0600, John Marvin wrote:
...
> No PA machine actually implements more
> than a 40 bit physical address space (even the latest Pluto based
> machines, which support 44 bits for IA64 are put into a 40 bit addressing
> mode for PARISC).

I was just looking at the pluto "PA_RISC Physical Address Map" and
all RAM is physically located < 1TB (40 bits).
Do we have to worry about the GMMIO (MMIO space above 4GB) in
"F-space" above 1TB?

The per rope 64KB IO Port space is accessed via the GMMIO address ranges.
This is in addition to the "global" IO Port space accessed through the
regular < 4GB MMIO address space. I'm guessing this won't ever need
to be mapped to userspace (or something like that), but just would
like to hear from someone who understands it better whats up.

That's for ZX1+PA8800. I've not looked SX1000 (Superdome).

thanks,
grant