[parisc-linux] itlb miss handler optimizations!

[Joel Soete]

>This fill the delayed branch slot (a silly idea, but ...)

Ha Ok (yet another concept for me ;-).  I will look for into architecture
books)

For the moment I am studying TLB miss handling and already have a lot of
questions.

But the very first one: H/W or S/W management (I refer to page 3-9 parisc-2.0:
Adress Resolution and the TLB)?

In the 2 cases, if a fault occurs an interrupt (6, 15, 16,17 or 20) is 'triggered'?

Is a printk() in corresponding handle_interruption() case (kernel/traps.c)
would help?
(if that work, how may I know which processor causes fault?)

Thanks again,
    Joel


-------------------------------------------------------------------------
Tiscali ADSL, seulement 35 eur/mois et le modem est inclus...abonnez-vous!
http://reg.tiscali.be/default.asp?lg=fr