[parisc-linux] Broken Cache Flushing in arch/parisc/kernel/signal.c.??

[Randolph Chung]

> +#if CACHE_FLUSHING_IS_NOT_BROKEN
>  	flush_icache_range((unsigned long) &frame->tramp[0],
>  			   (unsigned long) &frame->tramp[4]);
> +#else
> +       /* It should *always* be cache line-aligned, but the compiler
> +           sometimes screws up. */
> +       asm volatile("fdc 0(%%sr3,%0)\n\t"
> +                    "fdc %1(%%sr3,%0)\n\t"
> +                    "sync\n\t"
> +                    "fic 0(%%sr3,%0)\n\t"
> +                    "fic %1(%%sr3,%0)\n\t"
> +                    "sync\n\t"
> +                    : : "r" (frame->tramp), "r" (L1_CACHE_BYTES));
> +#endif
> +

<sigh>
this is partly my fault, since i thought we have unbroken cache flushing
and asked thibaut to check this in... now i see that the original code
flushes sr3 space, but flush_icache_range() flushes the kernel space...
oops!

perhaps we should just check the old code back in for now?

randolph
-- 
Randolph Chung
Debian GNU/Linux Developer, hppa/ia64 ports
http://www.tausq.org/