[parisc-linux] glibc 2.3.1 - It's alive! - patches

[John David Anglin]

> > __asm__ __volatile__ ("fmpy,dbl %1,%%fr0,%0\n\t"
> > 			/* FIXME: is this a proper trap barrier? */
> > 			"fcpy,dbl %%fr0,%%fr0" : "=f" (d) : "0"(d));
> 
> Looking at fraiseexcept, I see that you only want to raise one
> exception at a time out of a specified set.  Reading the status register
> will raise all outstanding exceptions.  I think what needs to be
> done is something like the following:

After a night's sleep, I had a couple more thoughts on this.

1) You probably want to clear the T bit at the beginning of the
   routine.  This will ensure that you get the correct exception
   when the first one is raised.  The only way to do this without
   potentially causing a pending trap to trigger is with a double
   word store to floating-point register 0.  You can't read register
   0 before the write without potentially triggering a trap, so
   you need to know what the current state should be.  See page
   10-5 of the PA2 arch manual.

2) A fcpy insn should raise an exception if it depends on the
   result of a pending trapping insn (the current code doesn't).
   It would be best to not use register 0 or the source register
   for the destination register since in theory the processor
   would then know the operation is a nop.  Then, the insn could
   be reordered or discarded.  The fcpy insn is nice since it
   is non-arithmetic and doesn't cause an invalid operation
   exception when a NaN is copied.  The fcmp insn isn't quite
   as nice since it will generate an invalid operation when one
   of the values is a signaling NaN, or if the low-order bit
   of the condition code is 1 and one of the values is an NaN.

Dave
-- 
J. David Anglin                                  dave.anglin@nrc.ca
National Research Council of Canada              (613) 990-0752 (FAX: 952-6605)