[parisc-linux] [patch 2/2] backport of sba sg list management to ccio-dma

[Grant Grundler]

On Wed, Nov 28, 2007 at 09:25:51AM +0100, Joel Soete wrote:
> > You need to read about "VIVT" caches (Virtual Indexed, Virtual Tagged).
> > The "Virtual Index" bits have to be provided by any cache coherent traffic
> > in order to be cache coherent. That's how the caches know _where_ in the
> > cache to find potential hits for a given cacheline.
> >
> For sure I need more reading but imho this paper is already clear on subject:
> my understanding (in short terms) is that cpu cache entry should be the same
> virtual address as DMA cache else it would need additional stuff to check
> physical address, right?

There is no "DMA Cache". The CPU owns the data cache and it needs enough
info to verify if particular DMA transactions affect entries in the
CPU cache (or not). "VIVT" summarizes the type of cache and thus info
the CPU needs for DMA/cache coherency checking.

cheers,
grant