[parisc-linux] [patch 2/2] backport of sba sg list management to ccio-dma

[Joel Soete]

> On Wed, Nov 28, 2007 at 09:25:51AM +0100, Joel Soete wrote:
> > > You need to read about "VIVT" caches (Virtual Indexed, Virtual Tagged).
> > > The "Virtual Index" bits have to be provided by any cache coherent traffic
> > > in order to be cache coherent. That's how the caches know _where_ in the
> > > cache to find potential hits for a given cacheline.
> > >
> > For sure I need more reading but imho this paper is already clear on subject:
> > my understanding (in short terms) is that cpu cache entry should be the same
> > virtual address as DMA cache else it would need additional stuff to check
> > physical address, right?
> 
> There is no "DMA Cache". The CPU owns the data cache and it needs enough
> info to verify if particular DMA transactions affect entries in the
> CPU cache (or not). "VIVT" summarizes the type of cache and thus info
> the CPU needs for DMA/cache coherency checking.
> 
> cheers,
> grant
> 
> 
mmm ok

I was confused by this:
[snip]
I/O Adapter Requirements
[snip]
Another demand ... It was decided that the new memory controller would not
implement writes of less than four words. (These types of writes would have
required read-modify-write operations in the DRAM array, which have long cycle
times and, if executed frequently, degrade overall main memory performance.)
Because one-word writes occur in the I/O system, for registers, semaphores, or
short DMA writes it was necessary that the I/O adapter implement a
one-line-deep cache to buffer cache lines, so that these one-word writes could
be executed by performing a coherent read private transaction on the Runway
bus, obtaining the most recent copy of the cache line, modifying it locally in
cache, and finally writing the modified line back to main memory. For the I/O
adapter to support a cache on the Runway bus, it has to have the ability to
compare processor-generated virtual address transactions with the address
contained in its cache to ensure that the processors always receive the most
up-to-date data.
[snip]

So thanks for your addtional comment, that would certainly help me to read
back this paper with another point of vue.

Tx,
    J.


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