[parisc-linux] Can't write to hard drives on a K200

[Michael S. Zick]

On Wed October 11 2006 20:19, Grant Grundler wrote:
> On Wed, Oct 11, 2006 at 11:14:13AM -0500, Michael S. Zick wrote:
> > Could you (or anyone on the list) eyeball the GSC scsi card(s) and
> > see if they have their own crystal(s)? 
> > Or are these controllers clocked by the GSC bus clock?
> > 
> > Expected would be a 40 or 80 Mhz crystal depending on the controller
> > if not clocked by the card's bus.
> 
> The GSC bus and the SCSI bus are in independent frequency domains.
>

Yes

> All logic on the board will be divided between those two zones.
> My guess is the SCSI chip is bridging the two but I don't know that
> for sure.

Correct - it is the chip's divider setting I am checking.

> 
> My point is the presence of the crystal is just to drive the clocking
> on the SCSI Bus 
>

Correct.  To get a 10Mhz scsi bus from a 40Mhz clock - you divide by 4.
If it is from a crystal on the card, does not matter where you plug in
the card.  

If it comes from the GSC bus clock and the GSC bus is one
that runs at 40 Mhz - you divide by 4 and get a 10 Mhz scsi bus.

If it comes from the GSC bus clock and the GSC bus is one
that runs at 32 Mhz - you divide by 4 and end up with a 8 Mhz scsi bus. 
This is just fine by the scsi spec - you are allowed to run a 10Mhz scsi 
bus system at 8Mhz.  

According to the wiki, some machines have _both_ speed buses.
See also: thread subject.

Your next step is to program the transfer period divider - at
which point you can be off by one in selecting the transfer period step
within the limits requested in the message from the drive.

So I don't need the crystal frequency, just the knowledge of: "crystal 
present or not present" on the card.  Everything depends on that fact.

The current drivers have a heritage of *bsd - back from the days of
ISA and EISA buses (8Mhz) - more recently, from PCI buses (33Mhz).
The early HP machines, for non-PCI scsi, where none of the above.

So it really isn't an idle question if someone wanted to cold-start
these controllers.

Current drivers do not cold-start the controller, they warm-start it.

That is, they depend on the bios to have initialized the dividers.

On ISA and EISA machines, which these drivers date from, this setting
is both "correct and optimal" since you don't have that many choices.

In HP machines, since they can boot from any scsi controller, the PDC
firmware has set the dividers.  But the values will be "conservative
and safe" values (since it only has to read in the OS to boot) not
"correct and optimal".

Without public documentation or reverse engineering HP hardware,
firmware, or software - "conservative and safe" is the only sure
assumption that can be made.  
And yes Willy, that is a guess (A.K.A: Uninformed assumption).

Hence my interest in cold-starting the controller.
Hence my "present / not present" question on the crystal.

> and probably doesn't tell us much about 
> which frequency domain any particular part is unless you
> put an oscilloscope on the board
> 

Don't need the part's speed, it is in the technical manuals;
only want the "implied clock source" not the clock speed.
What can be seen by the eyeball can't be HP proprietary information.

> grant
> 
> 

Mike