[parisc-linux] CCIO dma io_command and related io_tlb format questions.
Joel Soete
soete.joel at scarlet.be
Mon Oct 9 03:41:11 MDT 2006
Hello Grant,
I back port the sba sg list manager in ccio-dma on my d380 (not enough time to
test c110).
On one hand, it seems to improve a bit ncr53c720 behaviour: tar/rm loop test
run longer (at least 2h in place of 5/10 min)
Otoh no change (may be even worse) for ncr53c710 and break secondary nic (the
setup of this card make panicing the system?)
That said, there are no public doc of this IO stuff and so I didn't change
those 2 hunks:
[snip]
static CCIO_INLINE void
ccio_clear_io_tlb(struct ioc *ioc, dma_addr_t iovp, size_t byte_cnt)
{
u32 chain_size = 1 << ioc->chainid_shift;
iovp &= IOVP_MASK; /* clear offset bits, just want pagenum */
byte_cnt += chain_size;
while(byte_cnt > chain_size) {
WRITE_U32(CMD_TLB_PURGE | iovp, &ioc->ioc_regs->io_command);
iovp += chain_size;
byte_cnt -= chain_size;
}
}
[snip]
static void
ccio_ioc_init(struct ioc *ioc)
{
[snip]
/*
** Initialize all I/O TLB entries to 0 (Valid bit off).
*/
WRITE_U32(0, &ioc->ioc_regs->io_tlb_entry_m);
WRITE_U32(0, &ioc->ioc_regs->io_tlb_entry_l);
for(i = 1 << CCIO_CHAINID_SHIFT; i ; i--) {
WRITE_U32((CMD_TLB_DIRECT_WRITE | (i << ioc->chainid_shift)),
&ioc->ioc_regs->io_command);
}
}
...
About which cames to me 2 questions:
1/ what is supposed to contain an io_tlb entry: a io (page size) address
as seems to say the value ("CMD_TLB_PURGE | iovp")
in ccio_clear_io_tlb() or a memory page size should be splited in
severall tlb entries per ioc->chainid_shift?
2/ what is supposed to contain the ccio io_command register, I mean that
I don't understand what seems to me to be different io_command
contents for CMD_TLB_DIRECT_WRITE or CMD_TLB_PURGE?
If you still have (or access to) this internal doc, it would be great if you
could find some time to explain me those stuff.
TIA,
Joel
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