[parisc-linux] Heavy Iron Reference Docs

[Grant Grundler]

On Sun, Apr 30, 2006 at 06:28:26PM -0500, Michael S. Zick wrote:
> On Sun April 30 2006 18:01, Michael S. Zick wrote:
> > 
> > Scratches head...
> > 
> > I wonder where Joel has his processors installed in relation to the
> > two busses?  Both on same buss or one per buss?  Would his lockups
> > go away if he picked the other relationship?
> > 
> > I will ask him.  (or perhaps I just did)
> >
> 
> Browsing old parisc spinlock code, I find a comment that the N4K
> can only have one outstanding PxTLB transaction at a time.

The original document says:
	The Merced bus is designed to only support a single broadcast
	PxTLB transaction in progress at a time, and this must be guaranteed
	by software. Software must semaphore to guarantee that only one
	processor is trying to issue a broadcast PxTLB at a time.

	Local PxTLBs, however, have no restrictions, since they are executed
	entirely on the issuing processor.

> Is it not the PxTLB transactions that implement the inter-processor
> coherency?

I don't think so.

> 
> Which is of course required for inter-processor spinlocks to work.
> 
> And, of course, this being Linux, the queue is protected by a spinlock!

PA-RISC _only_ has a spinlock.

> Did someone just shoot themselves in the foot?

Do you honestly think the HP HW engineers were _that_ stupid?

They occasionally make mistakes....but designing an SMP machine
that doesn't have at least one working atomic op would be a bit
over the top. ;)

grant