[parisc-linux] The problem on the PA8800 is all in the data-cache.

[Grant Grundler]

On Mon, Jul 24, 2006 at 09:10:04AM -0500, James Bottomley wrote:
> What Matthew means is that the L2 cache is PIPT ... you can't get
> aliasing effects in a PIPT cache, so for the purposes of the problem it
> must be ignorable, since we can only get aliasing effects in the L1
> cache which is VIPT.

While I agree in general that a PIPT cache won't have aliasing effects.
ISTR the virtual coherence index (VCI) is part of the "physical address".
If it's not, I'm confused how CPUs on different sockets remain coherent.
I expect the VCI is visible across the Mckinley Bus and thus is part
of the physical address. IOMMU is also pushing out an address that
has VCI bits in it - so DMA remains coherent with CPU virtual addresses.

If I've got this right, then we can have aliasing in PIPT cache.
Willy, can you check the pa8800 ERS and look for "coherence index"
or similar, related words?

thanks,
grant