[parisc-linux] Re:[parisc-linux-cvs] linux-2.6 kyle

Joel Soete soete.joel at scarlet.be
Wed Aug 23 10:45:47 MDT 2006


> > That is the document that Dave drew from with his experimental patch.
> > I do not recall exactly which parts of those spinlocks routines he
> > included - perhaps he could update this thread on the subject.
> > 
> > When Joel tested Dave's patch to 128-byte align the static spinlocks,
> > he found the system ran longer (twice as long) before failing but the
> > failure still happened.
> 
> I'll just say that I don't think the answer to the soft lockup problem
> lies in the referenced document.  It contains a couple of interesting
> tricks.  However, I didn't find that the trick to dirty a cache line
> using the stby instruction helped on the machine that I tested on.
> I'm fairly certain that ldcw always runs in cache on PA 2.0 hardware.
> 
That was what I believed to have understood too.
(the idea was so that sync would force the write back to ram but then I read
more about memory strongly/weakly ordering and so became less sure?)
 
--- snip ---
> 
> As to Joel's problem, it's my personal opinion that the soft lockup
> problem is a simple deadlock.  An interrupt occurs on a cpu holding
> the lock and the ISR spins trying to reacquire the lock.
(just for my remind ISR == Interupt service routine)

--- snip ---

> 
> I did send to Kyle the portion of the patch used in the above test.
> It updated pdc.h and slightly changed the cache info displayed
> at boot and by /proc/cpuinfo.  It corrected a few bit fields and the
> difference between the I and D data structures.
> 
Nice ;-)

Cheers,
    Joel

> Dave
> -- 
> J. David Anglin                                  dave.anglin at nrc-cnrc.gc.ca
> National Research Council of Canada              (613) 990-0752 (FAX: 952-6602)
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> 

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