[parisc-linux] cacheline size and IPI

[Grant Grundler]

On Tue, Aug 22, 2006 at 06:00:38PM +0200, Joel Soete wrote:
> > No it can't. The CPU and memory controller have to agree on one size
> > for any given implementation. The IOMMU has to use this cacheline size
> > as well.
> >
> I doubt it could be important but is there a way to know the size of the
> cacheline 'negociated' between cpu and mc?

The cacheline size is decided by the HW designers.
Not negotiated at run time.

> PS: I forgot to ask: can you tell me in very short what IPI means in the linux
> kernel (iirc also related to spinlock management)?

Inter Processor Interrupt.
When one CPU wants to get the attention of another CPU and ask it
to do some house keeping work.

grant