[parisc-linux] Re:[parisc-linux-cvs] linux-2.6 kyle

[Grant Grundler]

On Tue, Aug 22, 2006 at 04:37:29PM +0200, Joel Soete wrote:
> I would like to thank all of you for kind advises: they help me to understand
> some stuff a bit more:
>   1/ "central bus" manage arbitration in such situation,

ldcw forces access to memory. The mem transaction has to go across some bus.
I call it the "central" bus since the exact type of bus depends
on the platform. All PA8[02567]00 CPUs connect to "Runway".
But "Merced" Bus is the "central" bus for N-class with many seperate
Runway busses in the platform.

>   2/ a 'cache line' is the smallest memory cache block which can be transfered
>      between ram and cache?

"cacheline" is the only transaction size many (not all) of the parisc
memory controllers will accept. If the system has an IOMMU, I expect
the memory controller to _only_ deal with cachelines.

I'm pretty sure uncached CPU accesses (e.g. ldwa) only work for MMIO space
and will be ignored by (or cause a fatal error in) the memory controller.


>   3/ from cpu view this cache line can be of 16, 32, 64 bytes
>      (may be 128 for newer) in length but that's the memory controler
>      of the "central bus" which give the actual value?

No it can't. The CPU and memory controller have to agree on one size
for any given implementation. The IOMMU has to use this cacheline size
as well.

> well it seems that I also missed an important detail: the 2 smp I am trying
> are pa8000 (d380) and pa8600 (n4k), i.e. all pa2.0 family which afaik are all
> weakly ordered?

No. Search our mail archive for "weak ordering".
PA20 Arch _allows_ weak ordering but no implmentation was ever made.

hth,
grant