[parisc-linux] Re:[parisc-linux-cvs] linux-2.6 kyle

[Michael S. Zick]

On Thu August 17 2006 03:02, Joel Soete wrote:
> 
> One more question (according to assembly stuff)
> what happen when the two cpu excute at the same time the same:
> 
>  ldcw,co 0(%r3),%r28 
> 

For your machine (not a McKinney bus) - See:
http://www.morethan.org/parisc/pa-spinlocks.html#tth_sEc4.1.3

Just ignore the couple of rows for the instructions that are
not in the Linux loop.

> here it seems that r3 are all == r26 == 000000001049ee80 
>

And r28 == 0 (locked), the r3 == r26 must have gotten set outside of the loop.

> (the idea is that: if the two cpu execute the same insn of the same loop at
> the same time they would also excecute at the same time the (2) previous insn) 
> 

In general, the bus is given to each cpu in round robin order for non-coherent
instructions.  

For your machine (not a McKinney bus) - See the runway bus rules in:
 http://ftp.parisc-linux.org/docs/chips/astro_runway.ps

For the gory details.

> (unfortunately I don't understand all the details of the ldcw description in
> parisc-2.0.pdf ;-( )
> 
> Sorry, a second question always about 
> static __inline__ __attribute__((always_inline)) void
> __raw_read_lock(raw_rwlock_t *rw)
> {
>  __raw_spin_lock_flags(&rw->lock, 0);
> 
>  rw->counter++;
> 
>  __raw_spin_unlock(&rw->lock);
> }
> 
> (and sisters)
> didn't we have to apply programming note page G4 (G-4 Memory Ordering Model
> PA-RISC 2.0 Architecture) with s ==  &rw->lock and x == rw->counter?
> 
> Thanks for your patience,
>     Joel
> 
Mike