[parisc-linux] Does it lakes some cloberred r1 in

[John David Anglin]

> Right, notice that it was at the request of HP-UX group for non-I/O
> devices.
> 
> Think of it this way:
> 
> ldcw, co Cache_Line[0]
> 
> The hardware, system wide, exclusive lock for this cache line.
> 
> A cache line is a big place...
> 
> ldcw, co Cache_Line[4 .. max-4]
> 
> This cpu now owns the cache line, so the other cpus do not need
> to be updated, nor the cache coherency bandwidth burned up...
> The non-zero cache line offset does this trick.

Ok, I understand.  I don't think that there is anything special
regarding Cache_Line[0].  You just need 4 bytes for the system-wide
lock.  Then, you can use the rest for semaphores on the cpu that
grabbed the system-wide lock.

Don't know if this trick would be useful for linux or not.

Dave
-- 
J. David Anglin                                  dave.anglin at nrc-cnrc.gc.ca
National Research Council of Canada              (613) 990-0752 (FAX: 952-6602)