[parisc-linux] Does it lakes some cloberred r1 in

[John David Anglin]

> ldcw,co target_address
> 
> Where target_address includes the magic byte[0] of 
> the cache line.

Where is this documented?

> Translation:
> 
> Spin on the ldcw,co not the ldw here.

I believe this makes sense as the errata specifies that the ldcw,co
operation has to be performed in cache on PA 2.0 machines:
http://h21007.www2.hp.com/dspp/tech/tech_TechDocumentDetailPage_IDX/1,1701,5310,00.html

> On the systems with 128 byte long cache lines,
> ensure these spinlocks are 128 byte aligned not
> 64 byte aligned as in this dump.

As a practical note, this is very difficult to achieve for dynamically
allocated spinlocks.

The intent of the errata seems to be to relax the alignment requirement
for ldc[dw],co in cases where the spinlock is not being shared with a
non-coherent I/O device.  If spinlocks have to be aligned to the start
of a cacheline, there doesn't seem to be any point to the errata.

Dave
-- 
J. David Anglin                                  dave.anglin at nrc-cnrc.gc.ca
National Research Council of Canada              (613) 990-0752 (FAX: 952-6602)