[parisc-linux] Proposal for altering our Page Table layouts

[John Marvin]

> Allocate all page tables in ZONE_DMA.  On PA, this means that the
> physical address of every page table will be under 4GB, so we only
> need *four* bytes for all of the directory entries. (The flags I'm
> looking for are only in the PTE, we have plenty of extra space
> still for directory flags).

You don't need this restriction.  No PA machine actually implements more
than a 40 bit physical address space (even the latest Pluto based
machines, which support 44 bits for IA64 are put into a 40 bit addressing
mode for PARISC).  So, for a 4K page table size (12 bits), you only need
28 bits (40-12) to be able to address any possible 4K aligned physical
address.  This leaves you 4 bits for directory flags.  Since we only
currently use 1, you still have 3 to spare.

Note that you won't even need to incur an extra instruction in the
tlb miss handler to do the shift, because the deposit to clear the valid
bit can be converted to a zdep to both clear the bit(s) and shift. I
think you have to use a different target register in that case though.

John