[parisc-linux] Re: [parisc-linux-cvs] linux grundler

[John David Anglin]

> That's interesting from an architecture PoV.  From my recollection when jsm
> was debugging problems on the 710, PCX-S is the only processor which actually
> enforces the 16-byte alignment restriction on ldcw.  So _practically_, we
> don't need it unless we're supporting those old processors.

I am pretty sure that any PA 1.x machine needs the alignment.

> > +#ifdef CONFIG_PA20
> > +/* PA2.0 is not strongly ordered. ldcw enforces ordering
> > + * and we need to make sure ordering is enforced on the unlock too.
> > + */
> > +#define spin_unlock(x) \
> > +		__asm__ __volatile__ ("stw,o  %%sp,0(%0)" : : "r" (x) : "memory" )

If you change the above to

  __asm__ __volatile__ ("stw,ma  %%sp,0(%0)" : : "r" (x) : "memory")

it should work on both PA11 and PA20.  The ordered completer is only
PA 2.

> Actually... this may be a long-standing bug in our spinlocks.  There's nothing
> to prevent gcc reordering writes around this assignment.  We need a barrier()
> before the assignment, or maybe it'd be as well to do the assignment in an
> asm() statement.
> 
> >  #define spin_unlock_wait(x)     do { barrier(); } while(((volatile spinlock_t *)(x))->lock == 0)

I think the volatile provides the barrier in my suggested version.

Dave
-- 
J. David Anglin                                  dave.anglin@nrc-cnrc.gc.ca
National Research Council of Canada              (613) 990-0752 (FAX: 952-6605)