[parisc-linux] Re: [parisc-linux-cvs] linux carlos

[Joel Soete]

>> 
>The additional CPUs just reference (ie load) the shared data using
>the same address. AFAIK, a cacheline will get loaded as "shared clean"
>until someone writes to it - which is when the cacheline ping-pong
>starts.

Ok I will have to re-read and again and again (each world is very important
in this book all short-cut is fatal for a good understanding)

>> Can you tell me more: in a previous piminfo collected I got for CPU#3
(3
>> is the "address" of the second cpu)

>PAT PDC (L-/N-class and A500) have hard coded numbers for CPUs.
>parisc-linux only uses logical CPU numbers to avoid sparsely populated
>arrays. parisc-linux can get the  "Physical CPU #" from PAT PDC.
>See code inside USE_PAT_CPUID in arch/parisc/kernel/processor.c.
>You might hack that code a bit so you can correlate logic to physical
>CPU numbers.

(I would do so later), I mean i would like to find the 'psw' value in a piminfo
listing (whatever the form it is: oct, hex, bin) to learn more about cpu
status at the panic moment (sorry for confusion but English is not my mother
tongue and frequently i still have pb to make understand my thought:) )

Thanks again,
    Joel
 

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