[parisc-linux] Re: [parisc-linux-cvs] linux carlos

[Grant Grundler]

On Mon, Aug 25, 2003 at 12:03:20PM +0200, Joel Soete wrote:
> So I would like to study now the early boot process
> (specialy for the second cpu) to try to understand how caches (for shared
> insn and data) are replicated into other CPU's [id]tlb.

The additional CPUs just reference (ie load) the shared data using
the same address. AFAIK, a cacheline will get loaded as "shared clean"
until someone writes to it - which is when the cacheline ping-pong
starts.

> Can you tell me more: in a previous piminfo collected I got for CPU#3 (3
> is the "address" of the second cpu)

PAT PDC (L-/N-class and A500) have hard coded numbers for CPUs.
parisc-linux only uses logical CPU numbers to avoid sparsely populated
arrays. parisc-linux can get the "Physical CPU #" from PAT PDC.
See code inside USE_PAT_CPUID in arch/parisc/kernel/processor.c.
You might hack that code a bit so you can correlate logic to physical
CPU numbers.

grant