[parisc-linux] Affined IRQs.

[Matthew Wilcox]

On Mon, Aug 11, 2003 at 09:44:49AM -0600, Grant Grundler wrote:
> Interrupts can be direct at any one CPU.
> ia64 and parisc IPI use the same method as IO devices.
> 
> The code does a round-robin when assigning IO interrupts to CPUs.
> ie assign interrupts to a sequential order of the CPUs.
> 
> A minor improvement would be to round-robin based on device class.
> But I want this intelligence in user space, not the kernel.
> NUMA machines want interrupts directed at CPUs in the same node
> where the IO is "hosted".
> 
> > 2. If a CPU on an SMP system is stopped or its interrupts are blocked,
> > will its interrupts automatically be serviced on another online CPU,
> 
> no. The interrupt must be "manually" redirected to another CPU.
> 
> > due to their non-affining nature?
> 
> Not sure what you mean here.

I think there's some confusion here.  I would say that interrupts on
PA-RISC are strongly CPU-affine, but there is currently no mechanism 
for controlling that affinity.  One interrupt will always go to the CPU
it's been programmed for.

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