[parisc-linux] glibc 2.3.1 - It's alive! - patches

[John David Anglin]

> And from the comment it seems that DHD wasn't sure either :)
> I don't quite understand what is meant by specifying register 0L?

You just have to do a floating-point load/store to/from register
0/0L using a doubleword/word instruction.  See the arch manual and
the comments about specify register 0 near the bottom of each
instruction description.  0L is the left part of floating 
register 0.  Doing this as a volatile asm should force completion
of all previous floating-point instructions.

A store from register 0 (the floating point status register) is a
safe barrier but you need to provide a location to store to.

I don't believe "fcpy,dbl %%fr0,%%fr0" provides the barrier
that you want.  The floating-point coprocessor is not required to
execute instructions sequentially although they must appear
sequential to software.  The above insn is a nop and the coprocessor
could throw it away early in the pipeline.

Dave
-- 
J. David Anglin                                  dave.anglin@nrc.ca
National Research Council of Canada              (613) 990-0752 (FAX: 952-6605)