[parisc-linux] O_DIRECT on devices

[Matthew Wilcox]

On Mon, Jul 15, 2002 at 01:42:19AM -0600, Grant Grundler wrote:
> Randolph and I think most SMP bugs reported (and we seen ourselves)
> suggest a D-cache problem.

Entirely plausible.  PA has bigger virtually indexed caches than anyone
else, so we're more susceptible to cache aliasing bugs than anyone else.
It could be a missing flush somewhere in the arch-independent code.

> My theory is virtual addresses are flushed on one CPU but any data 
> accessed through an aliases on another CPU are not flushed. And then
> we end up with an inconsistency.

it's certainly possible... i don't claim to understand exactly how this
works, but my recollection is that some of the flush instructions are
cpu-local whereas others are global to the system.  you'd have to ask
jsm about it, really.

> We've been reading Documentation/cachetlb.txt and trying
> to understand what it says about virtually indexed caches.

It seems pretty straightforward to me... am I missing something?

> The other thing is we don't hit the problems with PA8500 - only PA8700.
> I'm guessing the aliasing or timing is quite different betweem the two.
> Maybe someone else knows more?

8700 has bigger caches than 8500 and more TLB entries, so it may be
easier to hit problems.

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