[parisc-linux] lasi scsi driver

[Philipp Rumpf]

> While the PA-RISC processor architecture supports the notion of a
> non-cacheable page, most HP memory systems do not - certainly not the
> most recent memory systems.

Can you give us a concrete list of broken memory systems ?

> If you set the U-bit on a main memory page and then reference the page,
> the processor will emit a sub-cacheline transaction and the memory system
> will do something bad (probably HPMC).

So there is a sub-cacheline transaction on Runway but current memory
controllers don't implement it ?

> So don't ever get in the situation where you need uncacheable main memory.

uncacheable main memory is the only sane way to deal with cache-incoherent
DMA - macros to flush the cache are both slower and harder to add to drivers
written with the assumption that dma is cache-coherent.

	Philipp Rumpf