[parisc-linux] lasi scsi driver

[willy@thepuffingroup.com]

On Fri, Mar 03, 2000 at 11:10:58AM -0800, Jerry Huck wrote:
> While the PA-RISC processor architecture supports the notion of a
> non-cacheable page, most HP memory systems do not - certainly not the
> most recent memory systems.  If you set the U-bit on a main memory page
> and then reference the page, the processor will emit a sub-cacheline
> transaction and the memory system will do something bad (probably
> HPMC).  Also, I can't find any architected interface that would let
> you test if a memory page could be accessed uncacheable.

That isn't necessarily a problem.  The interface requires the allocation
of pages which are coherent.  On recent architectures, it's possible to
allocate pages which are actually IO coherent.  On earlier architectures,
the same interface would return uncached pages.  The question is
whether there are any implementations which can do neither of the two
possibilities.