Tue, 16 Nov 1999 17:50:53 +0000 (GMT)
> Consistent with what the widely-used ports do in 2.2 (as far as I can see).
You mean x86
> It sure can help from a performance pov.
> > Ultrasparc makes good use of tlb bypass bits for this.
> We do have load/store word bypassing the TLB instructions, if that's what you
> mean. We also can fix one of SR1-SR3 in kernel mode to be the identical map
> if some phys->virt instructions shows up heavily in profiles.
On the ultrasparc it pays off in part by avoiding TLB miss/reloads
> The day the parisc port reaches the usage counts we can stop caring about
> getting Oops/Panic messages (especially if they were unexpected and happened
> on a system that seemed stable a long time before) I might agree to the "only".
And until then you map in 20 odd pages. BFD
> Note that 3.75 GB userspace isn't a problem with either. My A class looks
> pretty packed with 768 MB RAM so I doubt you could fit more than 1.75 GB in
> many pa1.1 boxes.