[hppa-linux] Qn on PA-RISC Page tables and TLB

[Grant Grundler]

Kumar wrote:
...
> 	Other interesting point to note is that PA-RISC does not
> 	define how many entries in the table etc. Very much unlike
> 	x86.

The CPU pdir can vary in size. For a HW walker, it must be allocated
in physically configuous memory, this pretty much fixes the size
once it's setup.

The size of the CPU PDIR is determined mostly by memory size, amount
of I/O space required (Legacy PA requires memory mapped I/O), and
some fudge factor. Sizing it to allow a HW walker find all physical
mappings is good for performance. I assume this also helps SW TLB
handlers by reducing hash collisions. However, I'm not the expert
on CPU pdir.

K, C-class, and T600 also have an I/O pdir. This is only useful for
systems with more than 4GB (3.75GB?) of physical memory since PA
(and current PCI devices) can only use 32-bits of addressing.
The I/O pdir size depends on how much I/O one wants to allow mapped
at any given time and it too must be physically contigous.
16/th to 8th of physical memory seems to be a pretty good rule of thumb.

For now, I would say ignore the I/O pdir until hppa-linux has a
login prompt. If the OS doesn't use the I/O pdir, it just implies
the DMA is not coherent with Processor activity - just like on
an x86 box. I haven't studied Linux I/O subsytem enough to know
where/how to integrate support for an I/O pdir. I hope the HP-UX
docs released help explain this - search for keyword "CDIO".

grant