[hppa-linux] Picky details of TLB fault handlers

[Michael Shalayeff]

Making, drinking tea and reading an opus magnum from Alan Cox:
> > HP-UX does exactly this sort of thing for handling many traps and
> > interrupts.  It is fairly expensive, though, since you have to have
> > a stack on which to save the IPSW/IIAQ and probably a bunch of other
> > registers, and it's too much messing around for a TLB miss.
> 
> I'm right in assuming its legal to swap the return address - so the TLB
> handler can do a short piece of TLB handling for a present page miss,
> then stash the return into the kernel stack and rfi into the page fault handler
> so it will in turn return to the user context ?

i'd say that a miss handler would not _ever_ exceed 100 instructions total time
to successfully lookup and insert a missing translation into a tlb and
using just shadowed registers, so by doing that w/ all the interrupts
disabled (and keeping some data in direct-mapped segment) no need
to save even a single bit of context (since it's all in the shadows).
then the handler can save the whole context and call pagefault() routine to
process a complex page fault (ie one that has no translation
in the page table), since the whole context is saved it's safe to
receive any other page faults and/or interrupts.

this schema was first implemented in the lites (and mklinux later).
doing this way is like simulating the hardware TLB walker as present
on certain machines (712 at least, maybe any 7100lc, HP help!?)
there are certain constraints on page table organization, but
doing so would greatly speed up the tlb-walker equipped machines,
leaving the rest still in the best shape possible.
building a tlb-walker-ONLY kernel (as an option) may save about 10 other
instructions.

cu

-- 
    paranoic mickey       (my employers have changed but, the name has remained)