[hppa-linux] Picky details of TLB fault handlers

[Bjorn Helgaas]

Christopher Neufeld wrote
>
>The PA-RISC 2.0 documentation says that a (software) TLB miss fault handler
>cannot use virtual addressing. OK, what constitutes an exit from the
>handler? Can you use virtual addressing after the last modification the
>handler makes to the TLB (perhaps after executing several instructions
>which don't require virtual addressing to load the pipeline), or do you
>have to execute an explicit return from interrupt?

I think you just have to make sure that you can recover from all the
TLB miss faults you might encounter.  In order to recover, you need the
program counter at the time the trap occurred.  If the PSW Q-bit was set
at the time of interruption, the PSW and program counter are captured in
the IPSW and IIA queues, and the PSW Q-bit is cleared.  When you do the
RFI to "return from interrupt", the PSW and program counter with which
to resume are taken from from the IPSW and IIA queues.

So the software TLB miss handler runs with the Q-bit off.  If another
interruption occurred with the Q-bit off, the IPSW and IIA queues
would still reflect the point of the original TLB miss, *not* the point
where the second interruption occurred, and you would have to think very
carefully about whether this is what you want.  If the second interruption
happened to be another TLB miss, you would not get the ISR/IOR (because
the Q-bit was off), so it would be pretty tough to handle it.

You can certainly save the IPSW and IIA queues somewhere, then turn on
the Q-bit, go virtual, and do your interrupt handling in virtual mode.
In this case, you will execute an RFI just in order to turn on the Q-bit,
but the program counter at which to resume will be somewhere in the
interrupt handler, not the point where the original interruption occurred.
When you eventually finish the interrupt handler, you look up your saved
IPSW and IIA queues and do another RFI to return "for real".

HP-UX does exactly this sort of thing for handling many traps and
interrupts.  It is fairly expensive, though, since you have to have
a stack on which to save the IPSW/IIAQ and probably a bunch of other
registers, and it's too much messing around for a TLB miss.

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Bjorn Helgaas   helgaas@rsn.hp.com  telnet 1-497-3069  (972)497-3069