[parisc-linux] Re: [parisc-linux-cvs] linux-2.6 jejb

[John David Anglin]

> Agreed. I will assert memory barriers are not required (parisc HW is
> strongly ordered) and we have to tell gcc/binutils it can't re-order
> memory accesses across critical region boundaries (ie lock/unlock). 
> I don't know how to implement the latter and if adding "memory" to the
> ldcw/stw (lock/unlock) asm instructions is sufficient, then let's do that.

Adding "memory" to the list of clobbers in an asm indicates to gcc
that the asm clobbers ALL memory.  Thus, this creates a barrier blocking
the migration of all instructions that access memory.  Internally,
we also have a RTL pattern "blockage" to stop migration of all
instructions.  We could have a builtin emit this RTL but at the moment
I don't think there's a way for user code to generate a blockage.
You would get pretty much the same effect by clobbering all registers
and memory.

Dave
-- 
J. David Anglin                                  dave.anglin at nrc-cnrc.gc.ca
National Research Council of Canada              (613) 990-0752 (FAX: 952-6602)