[parisc-linux-cvs] linux-2.6 jejb

[James Bottomley]

On Wed, 2004-08-18 at 01:44, Grant Grundler wrote:
> It's not clear to me how adding mb() to before the ldcw()
> fixes this problem since ldcw() is an asm().
> asm() is not instruction barrier?

It's not a gcc *memory* barrier.  That means gcc is free to load a
memory reference before the spin lock and then use it after.  That's
what was happening in the f_list case, and why adding mb fixes the
problem.

> mb() is a NOP on parisc because we have strongly ordered memory.
> 
> PA20 arch allows weakly ordered mem.
> John Marvin was clear all implementations are strongly ordered.
> (See the mail archive for discussion about this)

Well...I don't think it should be.  If we're going to keep the O bit
zero then our mb() should be

asm volatile("sync" : : : "memory");

because it will then be semantically correct should a weakly ordered
processor ever come along.  For a strongly ordered processor, this is
almost a nop anyway...

James