[parisc-linux-cvs] linux-2.6 tausq

[Grant Grundler]

On Sat, Nov 01, 2003 at 08:51:50PM -0800, Randolph Chung wrote:
> +			/* Stack is 64-byte aligned, and we only 
> +			 * need to flush 1 cache line */
> +			asm("fdc 0(%%sr3, %0)\n"
> +			    "fic 0(%%sr3, %0)\n"
> +			    "sync\n"
> +			    : : "r"(regs->gr[30]));

John (Marvin), Lamont,
Does this sequence need a "sync" between the fdc/fic?

I see the following code in 2.4 arch/parisc/kernel/signal.c:
        /* It should *always* be cache line-aligned, but the compiler
           sometimes screws up. */
        asm volatile("fdc 0(%%sr3,%0)\n\t"
                     "fdc %1(%%sr3,%0)\n\t"
                     "sync\n\t"
                     "fic 0(%%sr3,%0)\n\t"
                     "fic %1(%%sr3,%0)\n\t"
                     "sync\n\t"
                     : : "r" (frame->tramp), "r" (L1_CACHE_BYTES));

But I have no clue if the first sync is really needed or not.

thanks,
grant