[parisc-linux-cvs] [PATCH] tulip update for the 3x5 HSC cards.

Grant Grundler grundler@dsl2.external.hp.com
Wed, 11 Sep 2002 10:31:52 -0600


Ryan Bradetich wrote:
> +			/* FIXME: this is WRONG! ggg says we need to poll bit 1
>   5 
> +			 * of Basic Mode Control register (address 00h) until i
>   t 
> +			 * is zero again.
> +			 * the right sequence in that code should be:
> +			 *   1) send reset_sequence[]
> +			 *   2) poll bit 15 until it's zero again
> +			 *   3) udelay(500)
> + 			 *   4) send init_sequence[]
> +			 * this based on the DP83840A Phy spec.
> +			 */

I worked this out and seems happy a500-44.
I still need to test on HP ZX1 systems or a500-65 where the
original problem was visible.

Please test and report problems back to me or ryan.

grant


Index: drivers/net/tulip/media.c
===================================================================
RCS file: /var/cvs/linux/drivers/net/tulip/media.c,v
retrieving revision 1.12
diff -u -p -r1.12 media.c
--- drivers/net/tulip/media.c	4 Aug 2002 22:58:40 -0000	1.12
+++ drivers/net/tulip/media.c	1 Sep 2002 02:24:35 -0000
@@ -277,16 +277,26 @@ void tulip_select_media(struct net_devic
 				int reset_length = p[2 + init_length];
 				misc_info = (u16*)(reset_sequence + reset_length);
 				if (startup) {
+					int timeout = 20;	/* 2 ms */
 					outl(mtable->csr12dir | 0x100, ioaddr + CSR12);
 					for (i = 0; i < reset_length; i++)
 						outl(reset_sequence[i], ioaddr + CSR12);
+
+					/* flush posted writes */
+					inl(ioaddr + CSR12);
+					/* Sect 3.10.3 in DP83840A.pdf (p39) */
+					udelay(500);
+
+					/* Section 4.2 in DP83840A.pdf (p43) */
+					while (timeout-- &&
+						(tulip_mdio_read (dev, phy_num, MII_BMCR) & BMCR_RESET))
+						udelay(100);
 				}
 				for (i = 0; i < init_length; i++)
 					outl(init_sequence[i], ioaddr + CSR12);
-			}
 
-			inl(ioaddr + CSR6);	/* flush posted writes */
-			udelay(500);
+				inl(ioaddr + CSR12);	/* flush posted writes */
+			}
 
 			tmp_info = get_u16(&misc_info[1]);
 			if (tmp_info)