[parisc-linux-cvs] Diff for recent submission

[John Marvin]

Here is the diff for a bug fix I just checked in. t0 was holding the
address of pa_dbit_lock in the 32 bit version of the PA2.0 dirty bit
handler. Some code was inserted later that wound up trashing t0,
causing us to take an unaligned fault with the Q bit off. I changed
all instances of the inserted code to use t1, rather than t0, although
only one instance was causing the problem.

This fixes the apt-get, smbd, etc. unaligned fault's we were seeing
on 32 bit SMP kernels run on PA2.0 boxes.

John

P.S. Finding the cause of faults that happen with the Q bit off can be
a little tricky :-)

--- arch/parisc/kernel/entry.S.old	Thu Oct 24 08:01:50 2002
+++ arch/parisc/kernel/entry.S	Thu Oct 24 08:06:31 2002
@@ -1319,9 +1319,9 @@
 
 	/* Get rid of prot bits and convert to page addr for idtlbt */
 
-	extrd,s         pte,35,4,t0
+	extrd,s         pte,35,4,t1
 	depdi		0,63,12,pte	/* clear lower 12 bits */
-        addi,=          1,t0,0 
+        addi,=          1,t1,0 
         extrd,u,*tr     pte,56,25,pte 
 	extrd,s		pte,56,25,pte	/* bit 31:8 >> 8  */ 
 	idtlbt          pte,prot
@@ -1389,9 +1389,9 @@
 
 	/* Get rid of prot bits and convert to page addr for idtlbt */
 
-        extrd,s         pte,35,4,t0
+        extrd,s         pte,35,4,t1
         depdi           0,63,12,pte     /* clear lower 12 bits */
-        addi,=          1,t0,0
+        addi,=          1,t1,0
         extrd,u,*tr     pte,56,25,pte
         extrd,s         pte,56,25,pte   /* bit 31:8 >> 8  */
         idtlbt          pte,prot
@@ -1642,9 +1642,9 @@
 
 	/* Get rid of prot bits and convert to page addr for iitlbt */
 
-        extrd,s         pte,35,4,t0 
+        extrd,s         pte,35,4,t1 
         depdi           0,63,12,pte     /* clear lower 12 bits */
-        addi,=          1,t0,0
+        addi,=          1,t1,0
         extrd,u,*tr     pte,56,25,pte 
         extrd,s         pte,56,25,pte   /* bit 31:8 >> 8  */
 	iitlbt          pte,prot
@@ -1860,9 +1860,9 @@
 	extrd,u,*= 	pte,_PAGE_GATEWAY_BIT+32,1,r0
 	depdi		0,11,2,prot	/* If Gateway, Set PL2 to 0 */
 
-        extrd,s         pte,35,4,t0 
+        extrd,s         pte,35,4,t1 
         depdi           0,63,12,pte     /* clear lower 12 bits */
-        addi,=          1,t0,0
+        addi,=          1,t1,0
         extrd,u,*tr     pte,56,25,pte 
         extrd,s         pte,56,25,pte   /* bit 31:8 >> 8  */
         idtlbt          pte,prot