[parisc-linux-cvs] linux grundler

Grant Grundler grundler@dsl2.external.hp.com
Sat, 25 May 2002 00:11:31 -0600


Grant Grundler wrote:
> Log message:
> 2.4.18-pa26 PA8700 enablement
> IO PDIR and CPU may not be coherent depending on platform.
> PDC tells us with PDC_MODEL CAPABILITIES call.
> tested on c3000 (PA8500) and rp24xx (PA8700).

diff is below.

BTW, I chose not to use self modifying code.
I've left the hooks in place for now but may remove those
if others agree with my reasoning. Having to trade off a function
call to avoid one cmp/branch didn't seem reasonable.

My next task is to rework the EIRR/EIM/I-bit handling.

grant

Index: Makefile
===================================================================
RCS file: /var/cvs/linux/Makefile,v
retrieving revision 1.296
diff -u -p -r1.296 Makefile
--- Makefile	2002/05/17 16:28:49	1.296
+++ Makefile	2002/05/25 05:39:26
@@ -1,7 +1,7 @@
 VERSION = 2
 PATCHLEVEL = 4
 SUBLEVEL = 18
-EXTRAVERSION = -pa25
+EXTRAVERSION = -pa26
 
 KERNELRELEASE=$(VERSION).$(PATCHLEVEL).$(SUBLEVEL)$(EXTRAVERSION)
 
Index: include/asm-parisc/pdc.h
===================================================================
RCS file: /var/cvs/linux/include/asm-parisc/pdc.h,v
retrieving revision 1.44
diff -u -p -r1.44 pdc.h
--- include/asm-parisc/pdc.h	2002/04/06 22:14:57	1.44
+++ include/asm-parisc/pdc.h	2002/05/25 05:39:26
@@ -504,6 +504,7 @@ struct pdc_model {		/* for PDC_MODEL */
 
 /* Values for PDC_MODEL_CAPABILITES non-equivalent virtual aliasing support */
 
+#define PDC_MODEL_IOPDIR_FDC            (1 << 2)        /* see sba_iommu.c */
 #define PDC_MODEL_NVA_MASK		(3 << 4)
 #define PDC_MODEL_NVA_SUPPORTED		(0 << 4)
 #define PDC_MODEL_NVA_SLOW		(1 << 4)
Index: arch/parisc/kernel/sba_iommu.c
===================================================================
RCS file: /var/cvs/linux/arch/parisc/kernel/sba_iommu.c,v
retrieving revision 1.66
diff -u -p -r1.66 sba_iommu.c
--- arch/parisc/kernel/sba_iommu.c	2002/04/05 08:02:02	1.66
+++ arch/parisc/kernel/sba_iommu.c	2002/05/25 05:39:26
@@ -40,8 +40,8 @@
 
 #include <linux/proc_fs.h>
 #include <asm/runway.h>		/* for proc_runway_root */
+#include <asm/pdc.h>		/* for PDC_MODEL_* */
 
-
 #define MODULE_NAME "SBA"
 
 /*
@@ -57,6 +57,14 @@
 #undef DEBUG_LARGE_SG_ENTRIES
 #undef DEBUG_DMB_TRAP
 
+/* XXX Need to determine if it's worth using self modifying code or not
+** in sba_dump_pdir_entry(). Avoids test/branch in critical code path.
+** But we have to eat a function call instead since sba_dump_pdir_entry()
+** is normally inline but can't be unless I figure out how to modify
+** three invocations. Right now, I think not.
+*/
+#undef SBA_SELF_MOD_CODE
+
 #define SBA_INLINE	__inline__
 
 #ifdef DEBUG_SBA_INIT
@@ -690,13 +698,17 @@ typedef unsigned long space_t;
  * We need to pre-swap the bytes since PCX-W is Big Endian.
  */
 
+
 void SBA_INLINE
 sba_io_pdir_entry(u64 *pdir_ptr, space_t sid, unsigned long vba)
 {
 	u64 pa; /* physical address */
 	register unsigned ci; /* coherent index */
 
-	/* We currently only support kernel addresses */
+	/* We currently only support kernel addresses.
+	 * fdc instr below will need to reload sr1 with KERNEL_SPACE
+	 * once we try to support direct DMA to user space.
+	 */
 	ASSERT(sid == KERNEL_SPACE);
 
 	pa = virt_to_phys(vba);
@@ -708,6 +720,19 @@ sba_io_pdir_entry(u64 *pdir_ptr, space_t
 
 	pa |= 0x8000000000000000ULL;	/* set "valid" bit */
 	*pdir_ptr = cpu_to_le64(pa);	/* swap and store into I/O Pdir */
+#ifdef SBA_SELF_MOD_CODE
+	asm("\nsba_iopdir_fdc:");
+	asm volatile("fdc 0(%%sr1,%0)\n\tsync" : : "r" (pdir_ptr));
+#else
+	/*
+	 * If the PDC_MODEL capabilities has Non-coherent IO-PDIR bit set
+	 * (bit #61, big endian), we have to flush and sync every time
+	 * IO-PDIR is changed in Ike/Astro.
+	 */
+	if (boot_cpu_data.pdc.capabilities & PDC_MODEL_IOPDIR_FDC) {
+		asm volatile("fdc 0(%%sr1,%0)\n\tsync" : : "r" (pdir_ptr));
+	}
+#endif
 }
 
 
@@ -1792,6 +1817,23 @@ sba_common_init(struct sba_device *sba_d
 	}
 
 	sba_dev->sba_lock = SPIN_LOCK_UNLOCKED;
+
+#ifdef SBA_SELF_MOD_CODE
+	/*
+	 * If the PDC_MODEL capabilities has Non-coherent IO-PDIR bit set
+	 * (bit #61, big endian), we have to flush and sync every time
+	 * IO-PDIR is changed in Ike/Astro.
+	 */
+	if (boot_cpu_data.pdc.capabilities & PDC_MODEL_IOPDIR_FDC) {
+		printk(KERN_INFO MODULE_NAME " FDC/SYNC needed\n");
+	} else {
+		extern unsigned int sba_iopdir_fdc;
+		printk(KERN_INFO MODULE_NAME " FDC/SYNC removed\n");
+		
+		((unsigned int *) &sba_iopdir_fdc)[0] = 0x08000240; /* NOP */
+		((unsigned int *) &sba_iopdir_fdc)[1] = 0x08000240; /* NOP */
+	}
+#endif
 }
 
 #ifdef CONFIG_PROC_FS