[parisc-linux-cvs] Re: U bit and memory mapped IO
Mon, 4 Mar 2002 04:40:54 -0700 (MST)
> > U bit is only necessary for F space access on PCXL2. It is not necessary
> > on any other processor.
> then the PA8000 in my C160 is sort of a strange CPU ? Without the U bit
> set it HPMCs, when accessing the framebuffer from userspace. I read the
> PA2.0 docs and there it is noted, that the behaviour of an unset U-bit for
> IO memory space is undefined.
Well, I can't explain what you are seeing. It might be interesting to
actually analyze the HPMC you are seeing.
Anyway, the architecture (both PA1.1 and PA2.0) allows for chips to
require the U bit for IO space. But only PCXL2 required it. You have to
refer to each CPU ers (which are not all currently available externally)
to find out the actual implementation. Here is what the PCXU (PA8000) cpu
3.3.2 Cache and the TLB U-bit
Software must guarantee pages with the TLB U-bit set are not in cache.
Accesses to U-bit data, except for some trapping behaviours, are
treated exactly like I/O accesses as far as the CPU core is concerned.
They are never issued speculatively. I/O pages can, but don't have
to have the U-bit set. PCXU will look at the real address as well as
the U-bit to determine if the address is treated as an I/O address.