[parisc-linux-cvs] [DIFF] 2.4.17-pa13 diff (IPV6)

[Grant Grundler]

Grant Grundler wrote:
...
> +	__asm__ __volatile__ (
> +
> +#if BITS_PER_LONG > 32
> +
> +	/*
> +	** We can execute two loads and two adds per cycle on PA 8000.
> +	** But add insn's get serialized waiting for the carry bit.
> +	** Try to keep 4 registers with "live" values ahead of the ALU.
> +	*/
> +
> +"	ldd,ma		4(%1), %%r19\n"	/* get 1st saddr word */
> +"	ldd,ma		4(%2), %%r20\n"	/* get 1st daddr word */

This is wrong. It should be 8(%1).  Fixed in 4 locations.

> +"	add		%4, %3, %3\n"/* add 16-bit proto + len */
> +"	add		%%r19, %0, %0\n"
> +"	ldd,ma		4(%1), %%r21\n"	/* 2cd saddr */
> +"	ldd,ma		4(%2), %%r22\n"	/* 2cd daddr */
...

grant