[parisc-linux-cvs] Cache line size fix

[Matthew Wilcox]

 * Make L1_CACHE_BYTES depend on CONFIG_PA20 instead of __LP64__
 * reorganise, tidy, fix comments

Index: include/asm-parisc/cache.h
===================================================================
RCS file: /home/cvs/parisc/linux/include/asm-parisc/cache.h,v
retrieving revision 1.11
diff -u -p -r1.11 cache.h
--- cache.h	2001/01/28 11:45:21	1.11
+++ cache.h	2001/03/17 04:52:45
@@ -5,28 +5,18 @@
 #ifndef __ARCH_PARISC_CACHE_H
 #define __ARCH_PARISC_CACHE_H
 
+#include <linux/config.h>
+
 #ifndef __ASSEMBLY__
 /*
-** XXX FIXME : L1_CACHE_BYTES (cacheline size) should be a boot time thing.
-** 
-** 32-bit on PA2.0 is not covered well by the #ifdef __LP64__ below.
-** PA2.0 processors have 64-byte cachelines.
-**
-** The issue is mostly cacheline ping-ponging on SMP boxes.
-** To avoid this, code should define stuff to be per CPU on cacheline
-** aligned boundaries. This can make a 2x or more difference in perf
-** depending on how badly the thrashing is.
-**
-** We don't need to worry about I/O since all PA2.0 boxes (except T600)
-** are I/O coherent. That means flushing less than you needed to generally
-** doesn't matter - the I/O MMU will read/modify/write the cacheline.
-**
-** (Digression: it is possible to program I/O MMU's to not first read
-** a cacheline for inbound data - ie just grab ownership and start writing.
-** While it improves I/O throughput, you gotta know the device driver
-** is well behaved and can deal with the issues.)
-*/
-#ifdef __LP64__
+ * PA 2.0 processors have 64-byte cachelines; PA 1.1 processors have
+ * 32-byte cachelines.  The default configuration is not for SMP anyway,
+ * so if you're building for SMP, you should select the appropriate
+ * processor type.  There is a potential livelock danger when running
+ * a machine with this value set too small, but it's more probable you'll
+ * just ruin performance.
+ */
+#ifdef CONFIG_PA20
 #define L1_CACHE_BYTES 64
 #else
 #define L1_CACHE_BYTES 32
@@ -38,7 +28,6 @@
 
 #define __cacheline_aligned __attribute__((__aligned__(L1_CACHE_BYTES)))
 
-
 extern void cache_init(void);		/* initializes cache-flushing */
 extern void flush_data_cache(void);	/* flushes data-cache only */
 extern void flush_instruction_cache(void);/* flushes code-cache only */
@@ -58,18 +47,17 @@ extern int split_tlb;
 extern int dcache_stride;
 extern int icache_stride;
 extern struct pdc_cache_info cache_info;
-#endif /* __ASSEMBLY__ */
 
+#define pdtlb(addr)         asm volatile("pdtlb 0(%%sr1,%0)" : : "r" (addr));
+#define pitlb(addr)         asm volatile("pitlb 0(%%sr1,%0)" : : "r" (addr));
+#define pdtlb_kernel(addr)  asm volatile("pdtlb 0(%0)" : : "r" (addr));
+
+#endif /* ! __ASSEMBLY__ */
+
 /* Classes of processor wrt: disabling space register hashing */
 
 #define SRHASH_PCXST    0   /* pcxs, pcxt, pcxt_ */
-#define SRHASH_PCXL     1   /* pcxl */
+#define SRHASH_PCXL     1   /* pcxl, pcxl2 */
 #define SRHASH_PA20     2   /* pcxu, pcxu_, pcxw, pcxw_ */
-
-#ifndef __ASSEMBLY__
-#define pdtlb(addr)         asm volatile("pdtlb 0(%%sr1,%0)" : : "r" (addr));
-#define pitlb(addr)         asm volatile("pitlb 0(%%sr1,%0)" : : "r" (addr));
-#define pdtlb_kernel(addr)  asm volatile("pdtlb 0(%0)" : : "r" (addr));
-#endif /* __ASSEMBLY__ */
 
 #endif