[parisc-linux-cvs] linux grundler
Grant Grundler
grundler@puffin.external.hp.com
Mon, 16 Jul 2001 18:32:14 -0600
Grant Grundler wrote:
> CVSROOT: /home/cvs/parisc
> Module name: linux
> Changes by: grundler 01/07/16 18:27:06
>
> Modified files:
> . : Makefile
> arch/parisc/kernel: lba_pci.c pci.c
> drivers/pci : pci.c setup-bus.c setup-res.c
> include/linux : ioport.h pci.h
Here's the matching diff.
grant
Grant Grundler
parisc-linux {PCI|IOMMU|SMP} hacker
+1.408.447.7253
Index: Makefile
===================================================================
RCS file: /home/cvs/parisc/linux/Makefile,v
retrieving revision 1.104
diff -u -p -r1.104 Makefile
--- Makefile 2001/07/15 18:49:15 1.104
+++ Makefile 2001/07/17 00:06:57
@@ -1,7 +1,7 @@
VERSION = 2
PATCHLEVEL = 4
SUBLEVEL = 6
-EXTRAVERSION = -pa19
+EXTRAVERSION = -pa20
KERNELRELEASE=$(VERSION).$(PATCHLEVEL).$(SUBLEVEL)$(EXTRAVERSION)
Index: arch/parisc/kernel/lba_pci.c
===================================================================
RCS file: /home/cvs/parisc/linux/arch/parisc/kernel/lba_pci.c,v
retrieving revision 1.29
diff -u -p -r1.29 lba_pci.c
--- lba_pci.c 2001/07/14 21:17:02 1.29
+++ lba_pci.c 2001/07/17 00:06:57
@@ -779,7 +779,11 @@ lba_fixup_bus(struct pci_bus *bus)
&bus->self->resource[PCI_BRIDGE_RESOURCES+i];
bus->resource[i]->name = bus->name;
}
+#if 0
bus->resource[0]->flags |= pci_bridge_check_io(bus->self);
+#else
+ bus->resource[0]->flags |= IORESOURCE_IO;
+#endif
bus->resource[1]->flags |= IORESOURCE_MEM;
bus->resource[2]->flags = 0; /* Don't support prefetchable */
bus->resource[3]->flags = 0; /* not used */
Index: arch/parisc/kernel/pci.c
===================================================================
RCS file: /home/cvs/parisc/linux/arch/parisc/kernel/pci.c,v
retrieving revision 1.22
diff -u -p -r1.22 pci.c
--- pci.c 2001/07/14 21:17:02 1.22
+++ pci.c 2001/07/17 00:06:57
@@ -18,13 +18,22 @@
#include <linux/string.h> /* for memcpy() */
#include <asm/system.h>
+#include <asm/cache.h> /* for L1_CACHE_BYTES */
#include <asm/pdc.h> /* for is_pdc_pat() macro */
#ifdef CONFIG_PCI
-#undef DEBUG_RESOURCES
+#define DEBUG_RESOURCES 0
+#define DEBUG_CONFIG 1
-#ifdef DEBUG_RESOURCES
+#if DEBUG_CONFIG
+# define DBGC(x...) printk(x)
+#else
+# define DBGC(x...)
+#endif
+
+
+#if DEBUG_RESOURCES
#define DBG_RES(x...) printk(x)
#else
#define DBG_RES(x...)
@@ -73,7 +82,7 @@ u##size in##type (int addr) \
ASSERT(pci_port); /* make sure services are defined */ \
ASSERT(parisc_pci_hba[b]); /* make sure ioaddr are "fixed up" */ \
if (parisc_pci_hba[b] == NULL) { \
- printk(KERN_WARNING "\nPCI or WAX Host Bus Adapter %d not registered. in" #size "(0x%x) returning -1\n", b, addr); \
+ printk(KERN_WARNING "\nPCI or EISA Host Bus Adapter %d not registered. in" #size "(0x%x) returning -1\n", b, addr); \
} else { \
d = pci_port->in##type(parisc_pci_hba[b], PCI_PORT_ADDR(addr)); \
} \
@@ -250,7 +259,7 @@ pcibios_update_resource(
== (PCI_BASE_ADDRESS_SPACE_MEMORY
| PCI_BASE_ADDRESS_MEM_TYPE_64)) {
pci_write_config_dword(dev, where+4, 0);
- printk(KERN_WARNING "PCI: dev %s type 64-bit\n", dev->name);
+ DBGC(KERN_INFO "PCI: dev %s type 64-bit\n", dev->name);
}
}
@@ -273,17 +282,44 @@ void
pcibios_set_master(struct pci_dev *dev)
{
u8 lat;
+
+ /* If someone already mucked with this, don't touch it. */
pci_read_config_byte(dev, PCI_LATENCY_TIMER, &lat);
if (lat >= 16) return;
/*
** HP generally has fewer devices on the bus than other architectures.
+ ** upper byte is PCI_LATENCY_TIMER.
*/
- printk(KERN_INFO "PCIBIOS: Setting latency timer of %s to 128\n", dev->slot_name);
- pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0x80);
+ pci_write_config_word(dev, PCI_CACHE_LINE_SIZE,
+ (0x80 << 8) | (L1_CACHE_BYTES / sizeof(u32)));
}
+void __init
+pcibios_init_bus(struct pci_bus *bus)
+{
+ struct pci_dev *dev = bus->self;
+
+ /* We deal only with pci controllers and pci-pci bridges. */
+ if (dev && (dev->class >> 8) != PCI_CLASS_BRIDGE_PCI)
+ return;
+
+ if (dev) {
+ /* PCI-PCI bridge - set the cache line and default latency
+ (32) for primary and secondary buses. */
+ pci_write_config_byte(dev, PCI_SEC_LATENCY_TIMER, 32);
+
+ /* Read bridge control */
+ pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &bus->bridge_ctl);
+ }
+
+ /* Set FBB bit for now. Disable ISA IO forwarding. Enable PERR/SERR */
+ bus->bridge_ctl |= PCI_BRIDGE_CTL_FAST_BACK |
+ PCI_BRIDGE_CTL_PARITY | PCI_BRIDGE_CTL_SERR;
+}
+
+
/*
** KLUGE: Link the child and parent resources - generic PCI didn't
*/
@@ -390,7 +426,7 @@ pcibios_align_resource(void *data, struc
int __devinit
pcibios_enable_device(struct pci_dev *dev)
{
- u16 cmd, old_cmd;
+ u16 cmd;
int idx;
/*
@@ -398,12 +434,13 @@ pcibios_enable_device(struct pci_dev *de
** enable all the same bits. We just make sure they are here.
*/
pci_read_config_word(dev, PCI_COMMAND, &cmd);
- old_cmd = cmd;
/*
** See if any resources have been allocated
+ ** While "regular" PCI devices only use 0-5, Bridges use a few
+ ** beyond that for window registers.
*/
- for (idx=0; idx<6; idx++) {
+ for (idx=0; idx<DEVICE_COUNT_RESOURCE; idx++) {
struct resource *r = &dev->resource[idx];
if (r->flags & IORESOURCE_IO)
cmd |= PCI_COMMAND_IO;
@@ -412,7 +449,7 @@ pcibios_enable_device(struct pci_dev *de
}
/*
- ** System error and Parity Error reporting are enabled by default.
+ ** Enable System error and Parity Error reporting by default.
** Devices that do NOT want those behaviors should clear them
** (eg PCI graphics, possibly networking).
** Interfaces like SCSI certainly should not. We want the
@@ -421,13 +458,28 @@ pcibios_enable_device(struct pci_dev *de
*/
cmd |= (PCI_COMMAND_SERR | PCI_COMMAND_PARITY);
- if (cmd != old_cmd) {
- printk(KERN_INFO "PCIBIOS: Enabling device %s (%04x -> %04x)\n",
- dev->slot_name, old_cmd, cmd);
- pci_write_config_word(dev, PCI_COMMAND, cmd);
- }
+ /* If bridge/bus controller has FBB enabled, child must too. */
+ if (dev->bus->bridge_ctl & PCI_BRIDGE_CTL_FAST_BACK)
+ cmd |= PCI_COMMAND_FAST_BACK;
+ DBGC(KERN_INFO "PCIBIOS: Enabling device %s cmd 0x%04x\n", dev->slot_name, cmd);
+ pci_write_config_word(dev, PCI_COMMAND, cmd);
return 0;
+}
+
+void __init
+pcibios_setup_host_bridge(struct pci_bus *bus)
+{
+ ASSERT(pci_bios != NULL);
+
+#if 0
+ if (pci_bios)
+ {
+ if (pci_bios->setup_host_bridge) {
+ (*pci_bios->setup_host_bridge)(bus);
+ }
+ }
+#endif
}
Index: drivers/pci/pci.c
===================================================================
RCS file: /home/cvs/parisc/linux/drivers/pci/pci.c,v
retrieving revision 1.13
diff -u -p -r1.13 pci.c
--- pci.c 2001/07/06 00:52:55 1.13
+++ pci.c 2001/07/17 00:06:57
@@ -1165,6 +1165,7 @@ static void pci_read_irq(struct pci_dev
int pci_setup_device(struct pci_dev * dev)
{
u32 class;
+ unsigned short status;
sprintf(dev->slot_name, "%02x:%02x.%d", dev->bus->number, PCI_SLOT(dev->devfn), PCI_FUNC(dev->devfn));
sprintf(dev->name, "PCI device %04x:%04x", dev->vendor, dev->device);
@@ -1212,6 +1213,11 @@ int pci_setup_device(struct pci_dev * de
dev->class = PCI_CLASS_NOT_DEFINED;
}
+ /* FBB capability - if not, clear bit in parent bridge_ctl. */
+ pci_read_config_word(dev, PCI_STATUS, &status);
+ if (!(status & PCI_STATUS_FAST_BACK))
+ dev->bus->bridge_ctl &= ~PCI_BRIDGE_CTL_FAST_BACK;
+
/* We found a fine healthy device, go go go... */
return 0;
}
@@ -1293,6 +1299,8 @@ static unsigned int __init pci_do_scan_b
unsigned int devfn, max, pass;
struct list_head *ln;
struct pci_dev *dev, dev0;
+
+ pcibios_init_bus(bus);
DBG("Scanning bus %02x\n", bus->number);
max = bus->secondary;
Index: drivers/pci/setup-bus.c
===================================================================
RCS file: /home/cvs/parisc/linux/drivers/pci/setup-bus.c,v
retrieving revision 1.8
diff -u -p -r1.8 setup-bus.c
--- setup-bus.c 2001/07/07 06:45:56 1.8
+++ setup-bus.c 2001/07/17 00:06:57
@@ -12,8 +12,14 @@
/*
* Nov 2000, Ivan Kokshaysky <ink@jurassic.park.msu.ru>
* PCI-PCI bridges cleanup, sorted resource allocation
- * Feb 2001, Grant Grundler <grundler@puffin.external.hp.com>
- * add __hppa__ klu^H^H^Hsupport.
+ * Jul 2001, Grant Grundler <grundler@puffin.external.hp.com>
+ * contribute FBB support, help w/arch cleanup
+ *
+ * NOTE: during reallocation we may have temporarily overlapping
+ * IO or MEM ranges, so the arch code (pcibios_fixup_bus()) is
+ * responsible for disabling all devices, probably except console
+ * (VGA, serial etc.) and bridges the console device might be
+ * behind -- typically AGP or PCI-(E)ISA bridges.
*/
#include <linux/init.h>
@@ -25,7 +31,7 @@
#include <linux/slab.h>
-#define DEBUG_CONFIG 1
+#define DEBUG_CONFIG 0
#if DEBUG_CONFIG
# define DBGC(args) printk args
#else
@@ -49,32 +55,8 @@ pbus_assign_resources_sorted(struct pci_
struct pci_dev *dev = pci_dev_b(ln);
u16 class = dev->class >> 8;
- /* First, disable the device to avoid side
- effects of possibly overlapping I/O and
- memory ranges.
- Leave VGA enabled - for obvious reason. :-)
- Same with all sorts of bridges - they may
- have VGA behind them. */
- if (class == PCI_CLASS_DISPLAY_VGA
- || class == PCI_CLASS_NOT_DEFINED_VGA)
- found_vga = 1;
-#ifndef __hppa__
-/*
-** If I/O or MEM ranges are overlapping, that's a BIOS bug.
-** Fix it in quirks?
-**
-** Disabling *all* devices is bad. Console, root, etc get
-** disabled this way.
-** -ggg
-*/
- else if (class >> 8 != PCI_BASE_CLASS_BRIDGE) {
- u16 cmd;
- pci_read_config_word(dev, PCI_COMMAND, &cmd);
- cmd &= ~(PCI_COMMAND_IO | PCI_COMMAND_MEMORY
- | PCI_COMMAND_MASTER);
- pci_write_config_word(dev, PCI_COMMAND, cmd);
- }
-#endif
+ found_vga = (class == PCI_CLASS_DISPLAY_VGA
+ || class == PCI_CLASS_NOT_DEFINED_VGA);
/* Reserve some resources for CardBus.
Are these values reasonable? */
@@ -142,6 +124,7 @@ pci_setup_bridge(struct pci_bus *bus)
if (!bridge || (bridge->class >> 8) != PCI_CLASS_BRIDGE_PCI)
return;
+
ranges.io_start = bus->resource[0]->start;
ranges.io_end = bus->resource[0]->end;
ranges.mem_start = bus->resource[1]->start;
@@ -193,33 +176,38 @@ pci_setup_bridge(struct pci_bus *bus)
}
pci_write_config_dword(bridge, PCI_PREF_MEMORY_BASE, l);
-#ifdef __hppa__
-/* XXX FIXME
-** PCI_BRIDGE_CONTROL and PCI_COMMAND programming need to be revisited
-** to support FBB. Make all this crud "configurable" by the arch specific
-** (ie "PCI BIOS") support and the ifdef __hppa__ crap can go away then.
-*/
- /*
- ** ISA stuff confuses PDC PAT configuration.
- ** VGA will probably crash the system at the moment.
- ** (Fortunately, only _A_ dares install VGA in a parisc box :^)
- ** - ggg
- */
- l = PCI_BRIDGE_CTL_PARITY | PCI_BRIDGE_CTL_SERR;
-#else
- /* Check if we have VGA behind the bridge.
- Enable ISA in either case. */
- l = (bus->resource[0]->flags & IORESOURCE_BUS_HAS_VGA) ? 0x0c : 0x04;
-#endif
- pci_write_config_word(bridge, PCI_BRIDGE_CONTROL, l);
+ /* If all devices on the bus and the bridge itself support FBB,
+ enable it. pci_enable_device() will enable FBB for devices. */
+ pci_read_config_word(bridge, PCI_SEC_STATUS, (u16 *)&l);
+ if (!(l & PCI_BRIDGE_CTL_FAST_BACK))
+ bus->bridge_ctl &= ~PCI_BRIDGE_CTL_FAST_BACK;
+ pci_write_config_word(bridge, PCI_BRIDGE_CONTROL, bus->bridge_ctl);
- pci_write_config_dword(bridge, PCI_COMMAND, 0xffff0007
-#ifdef __hppa__
- /* servers definitely want SERR/PERR enabled. */
- | PCI_COMMAND_SERR | PCI_COMMAND_PARITY
-#endif
- );
+ pci_enable_device(bridge);
+ pci_set_master(bridge);
+}
+
+
+/* Check whether the bridge supports I/O forwarding.
+ If not, its I/O base/limit register must be
+ read-only and read as 0. */
+static unsigned long __init
+pci_bridge_check_io(struct pci_dev *bridge)
+{
+ u16 io;
+
+ pci_read_config_word(bridge, PCI_IO_BASE, &io);
+ if (!io) {
+ pci_write_config_word(bridge, PCI_IO_BASE, 0xf0f0);
+ pci_read_config_word(bridge, PCI_IO_BASE, &io);
+ pci_write_config_word(bridge, PCI_IO_BASE, 0x0);
+ }
+ if (io)
+ return IORESOURCE_IO;
+ printk(KERN_WARNING "PCI: bridge %s does not support I/O forwarding!\n",
+ bridge->name);
+ return 0;
}
void __init
@@ -232,26 +220,47 @@ pbus_assign_resources(struct pci_bus *bu
struct pci_bus *b;
ranges->found_vga = 1;
- /* Propogate presence of the VGA to upstream bridges */
- for (b = bus; b->parent; b = b->parent) {
-#if 0
- /* ? Do we actually need to enable PF memory? */
- b->resource[2]->start = 0;
-#endif
- b->resource[0]->flags |= IORESOURCE_BUS_HAS_VGA;
- }
+ /* Propagate presence of the VGA to upstream bridges */
+ for (b = bus; b->parent; b = b->parent)
+ b->bridge_ctl |= PCI_BRIDGE_CTL_VGA;
}
for (ln=bus->children.next; ln != &bus->children; ln=ln->next) {
struct pci_bus *b = pci_bus_b(ln);
+ struct pci_dev *bridge = b->self;
+ int i;
+ /* Link bus resources to the bridge ones. */
+ for(i=0; i<3; i++) {
+ b->resource[i] =
+ &bridge->resource[PCI_BRIDGE_RESOURCES+i];
+ b->resource[i]->name = bus->name;
+ }
+ b->resource[0]->flags |= pci_bridge_check_io(bridge);
+ b->resource[1]->flags |= IORESOURCE_MEM;
b->resource[0]->start = ranges->io_start = ranges->io_end;
b->resource[1]->start = ranges->mem_start = ranges->mem_end;
+ /* For now, set IO and MEM limits of this bus
+ same as limits of its parent bus. */
+ b->resource[0]->end = bus->resource[0]->end;
+ b->resource[1]->end = bus->resource[1]->end;
+
pbus_assign_resources(b, ranges);
+ /* Adjust bus limits. */
b->resource[0]->end = ranges->io_end - 1;
b->resource[1]->end = ranges->mem_end - 1;
+ /* Add bridge resources to the resource tree. */
+ if (b->resource[0]->end > b->resource[0]->start &&
+ request_resource(bus->resource[0], b->resource[0]) < 0)
+ printk(KERN_ERR "PCI: failed to request IO "
+ "for bus %d\n", b->number);
+ if (b->resource[1]->end > b->resource[1]->start &&
+ request_resource(bus->resource[1], b->resource[1]) < 0)
+ printk(KERN_ERR "PCI: failed to request MEM "
+ "for bus %d\n", b->number);
+
pci_setup_bridge(b);
}
}
@@ -261,7 +270,6 @@ pci_assign_unassigned_resources(void)
{
struct pbus_set_ranges_data ranges;
struct list_head *ln;
- struct pci_dev *dev;
for(ln=pci_root_buses.next; ln != &pci_root_buses; ln=ln->next) {
struct pci_bus *b = pci_bus_b(ln);
@@ -272,29 +280,6 @@ pci_assign_unassigned_resources(void)
ranges.mem_end = ranges.mem_start;
ranges.found_vga = 0;
pbus_assign_resources(b, &ranges);
+ pcibios_setup_host_bridge(b);
}
- pci_for_each_dev(dev) {
- pdev_enable_device(dev);
- }
-}
-
-/* Check whether the bridge supports I/O forwarding.
- If not, its I/O base/limit register must be
- read-only and read as 0. */
-unsigned long __init
-pci_bridge_check_io(struct pci_dev *bridge)
-{
- u16 io;
-
- pci_read_config_word(bridge, PCI_IO_BASE, &io);
- if (!io) {
- pci_write_config_word(bridge, PCI_IO_BASE, 0xf0f0);
- pci_read_config_word(bridge, PCI_IO_BASE, &io);
- pci_write_config_word(bridge, PCI_IO_BASE, 0x0);
- }
- if (io)
- return IORESOURCE_IO;
- printk(KERN_WARNING "PCI: bridge %s does not support I/O forwarding!\n",
- bridge->name);
- return 0;
}
Index: drivers/pci/setup-res.c
===================================================================
RCS file: /home/cvs/parisc/linux/drivers/pci/setup-res.c,v
retrieving revision 1.10
diff -u -p -r1.10 setup-res.c
--- setup-res.c 2001/07/07 06:45:57 1.10
+++ setup-res.c 2001/07/17 00:06:57
@@ -177,58 +177,3 @@ pdev_sort_resources(struct pci_dev *dev,
}
}
}
-
-void __init
-pdev_enable_device(struct pci_dev *dev)
-{
- u32 reg;
- u16 cmd;
- int i;
-
- DBGC((KERN_ERR "PCI enable device: (%s)\n", dev->name));
-
- pci_read_config_word(dev, PCI_COMMAND, &cmd);
-
- for (i = 0; i < PCI_NUM_RESOURCES; i++) {
- struct resource *res = &dev->resource[i];
-
- if (res->flags & IORESOURCE_IO)
- cmd |= PCI_COMMAND_IO;
- else if (res->flags & IORESOURCE_MEM)
- cmd |= PCI_COMMAND_MEMORY;
- }
-
- /* Special case, disable the ROM. Several devices act funny
- (ie. do not respond to memory space writes) when it is left
- enabled. A good example are QlogicISP adapters. */
-
- if (dev->rom_base_reg) {
- pci_read_config_dword(dev, dev->rom_base_reg, ®);
- reg &= ~PCI_ROM_ADDRESS_ENABLE;
- pci_write_config_dword(dev, dev->rom_base_reg, reg);
- dev->resource[PCI_ROM_RESOURCE].flags &= ~PCI_ROM_ADDRESS_ENABLE;
- }
-
- /* All of these (may) have I/O scattered all around and may not
- use I/O base address registers at all. So we just have to
- always enable IO to these devices. */
- if ((dev->class >> 8) == PCI_CLASS_NOT_DEFINED
- || (dev->class >> 8) == PCI_CLASS_NOT_DEFINED_VGA
- || (dev->class >> 8) == PCI_CLASS_STORAGE_IDE
- || (dev->class >> 16) == PCI_BASE_CLASS_DISPLAY) {
- cmd |= PCI_COMMAND_IO;
- }
-
- /* ??? Always turn on bus mastering. If the device doesn't support
- it, the bit will go into the bucket. */
- cmd |= PCI_COMMAND_MASTER;
-
- /* Set the cache line and default latency (32). */
- pci_write_config_word(dev, PCI_CACHE_LINE_SIZE,
- (32 << 8) | (L1_CACHE_BYTES / sizeof(u32)));
-
- /* Enable the appropriate bits in the PCI command register. */
- pci_write_config_word(dev, PCI_COMMAND, cmd);
-
- DBGC((KERN_ERR " cmd reg 0x%x\n", cmd));
-}
Index: include/linux/ioport.h
===================================================================
RCS file: /home/cvs/parisc/linux/include/linux/ioport.h,v
retrieving revision 1.4
diff -u -p -r1.4 ioport.h
--- ioport.h 2001/01/25 00:03:17 1.4
+++ ioport.h 2001/07/17 00:06:57
@@ -40,7 +40,6 @@ struct resource_list {
#define IORESOURCE_CACHEABLE 0x00004000
#define IORESOURCE_RANGELENGTH 0x00008000
#define IORESOURCE_SHADOWABLE 0x00010000
-#define IORESOURCE_BUS_HAS_VGA 0x00080000
#define IORESOURCE_UNSET 0x20000000
#define IORESOURCE_AUTO 0x40000000
Index: include/linux/pci.h
===================================================================
RCS file: /home/cvs/parisc/linux/include/linux/pci.h,v
retrieving revision 1.8
diff -u -p -r1.8 pci.h
--- pci.h 2001/07/05 21:39:34 1.8
+++ pci.h 2001/07/17 00:06:57
@@ -429,6 +429,8 @@ struct pci_bus {
unsigned char productver; /* product version */
unsigned char checksum; /* if zero - checksum passed */
unsigned char pad1;
+ unsigned short bridge_ctl; /* manage NO_ISA/FBB/et al behaviors */
+ unsigned short pad2;
};
#define pci_bus_b(n) list_entry(n, struct pci_bus, node)
@@ -491,8 +493,10 @@ struct pci_driver {
#define pci_for_each_dev(dev) \
for(dev = pci_dev_g(pci_devices.next); dev != pci_dev_g(&pci_devices); dev = pci_dev_g(dev->global_list.next))
-void pcibios_init(void);
-void pcibios_fixup_bus(struct pci_bus *);
+/* pcibios_*() == arch specific implementation */
+void pcibios_init(void); /* global init */
+void pcibios_init_bus(struct pci_bus *); /* before each bus scan */
+void pcibios_fixup_bus(struct pci_bus *); /* after each bus scan */
int pcibios_enable_device(struct pci_dev *);
char *pcibios_setup (char *str);
@@ -502,6 +506,7 @@ void pcibios_update_resource(struct pci_
struct resource *, int);
void pcibios_update_irq(struct pci_dev *, int irq);
void pcibios_fixup_pbus_ranges(struct pci_bus *, struct pbus_set_ranges_data *);
+void pcibios_setup_host_bridge(struct pci_bus *);
/* Backward compatibility, don't use in new code! */
@@ -572,9 +577,7 @@ int pci_enable_wake(struct pci_dev *dev,
int pci_claim_resource(struct pci_dev *, int);
void pci_assign_unassigned_resources(void);
-void pdev_enable_device(struct pci_dev *);
void pdev_sort_resources(struct pci_dev *, struct resource_list *, u32);
-unsigned long pci_bridge_check_io(struct pci_dev *);
void pci_fixup_irqs(u8 (*)(struct pci_dev *, u8 *),
int (*)(struct pci_dev *, u8, u8));
#define HAVE_PCI_REQ_REGIONS