[parisc-linux-cvs] DIFF 2.4.16-pa30 update drivers/pci
Grant Grundler
grundler@dsl2.external.hp.com
Sat, 29 Dec 2001 20:35:43 -0700
Grant Grundler wrote:
> Log message:
> 2.4.16-pa30 update drivers/pci with latest diff from Ivan Kokshaysky
Index: Makefile
===================================================================
RCS file: /var/cvs/linux/Makefile,v
retrieving revision 1.234
diff -u -p -r1.234 Makefile
--- Makefile 2001/12/29 05:35:12 1.234
+++ Makefile 2001/12/29 21:23:21
@@ -1,7 +1,7 @@
VERSION = 2
PATCHLEVEL = 4
SUBLEVEL = 16
-EXTRAVERSION = -pa29
+EXTRAVERSION = -pa30
KERNELRELEASE=$(VERSION).$(PATCHLEVEL).$(SUBLEVEL)$(EXTRAVERSION)
Index: drivers/pci/pci.c
===================================================================
RCS file: /var/cvs/linux/drivers/pci/pci.c,v
retrieving revision 1.18
diff -u -p -r1.18 pci.c
--- drivers/pci/pci.c 2001/11/29 15:49:39 1.18
+++ drivers/pci/pci.c 2001/12/29 21:23:22
@@ -914,13 +914,15 @@ static void pci_read_bases(struct pci_de
l = 0;
if ((l & PCI_BASE_ADDRESS_SPACE) == PCI_BASE_ADDRESS_SPACE_MEMORY) {
res->start = l & PCI_BASE_ADDRESS_MEM_MASK;
+ res->flags |= l & ~PCI_BASE_ADDRESS_MEM_MASK;
sz = pci_size(sz, PCI_BASE_ADDRESS_MEM_MASK);
} else {
res->start = l & PCI_BASE_ADDRESS_IO_MASK;
+ res->flags |= l & ~PCI_BASE_ADDRESS_IO_MASK;
sz = pci_size(sz, PCI_BASE_ADDRESS_IO_MASK & 0xffff);
}
res->end = res->start + (unsigned long) sz;
- res->flags |= (l & 0xf) | pci_calc_resource_flags(l);
+ res->flags |= pci_calc_resource_flags(l);
if ((l & (PCI_BASE_ADDRESS_SPACE | PCI_BASE_ADDRESS_MEM_TYPE_MASK))
== (PCI_BASE_ADDRESS_SPACE_MEMORY | PCI_BASE_ADDRESS_MEM_TYPE_64)) {
pci_read_config_dword(dev, reg+4, &l);
Index: drivers/pci/setup-bus.c
===================================================================
RCS file: /var/cvs/linux/drivers/pci/setup-bus.c,v
retrieving revision 1.9
diff -u -p -r1.9 setup-bus.c
--- drivers/pci/setup-bus.c 2001/07/17 00:27:04 1.9
+++ drivers/pci/setup-bus.c 2001/12/29 21:23:22
@@ -12,10 +12,12 @@
/*
* Nov 2000, Ivan Kokshaysky <ink@jurassic.park.msu.ru>
* PCI-PCI bridges cleanup, sorted resource allocation
- * Jul 2001, Grant Grundler <grundler@puffin.external.hp.com>
- * contribute FBB support, help w/arch cleanup
- *
- * NOTE: during reallocation we may have temporarily overlapping
+ * Jul 2001, Grant Grundler <grundler@parisc-linux.org>,
+ * Ivan Kokshaysky <ink@jurassic.park.msu.ru>
+ * Further cleanup, generic Fast-Back-to-Back/PERR/SERR support
+ */
+
+/* NOTE: during reallocation we may have temporarily overlapping
* IO or MEM ranges, so the arch code (pcibios_fixup_bus()) is
* responsible for disabling all devices, probably except console
* (VGA, serial etc.) and bridges the console device might be
@@ -55,8 +57,8 @@ pbus_assign_resources_sorted(struct pci_
struct pci_dev *dev = pci_dev_b(ln);
u16 class = dev->class >> 8;
- found_vga = (class == PCI_CLASS_DISPLAY_VGA
- || class == PCI_CLASS_NOT_DEFINED_VGA);
+ found_vga |= (class == PCI_CLASS_DISPLAY_VGA ||
+ class == PCI_CLASS_NOT_DEFINED_VGA);
/* Reserve some resources for CardBus.
Are these values reasonable? */
@@ -94,20 +96,6 @@ pbus_assign_resources_sorted(struct pci_
ranges->io_end += io_reserved;
ranges->mem_end += mem_reserved;
- /* PCI-to-PCI Bridge Architecture Specification rev. 1.1 (1998)
- requires that if there is no I/O ports or memory behind the
- bridge, corresponding range must be turned off by writing base
- value greater than limit to the bridge's base/limit registers. */
-#if 1
- /* But assuming that some hardware designed before 1998 might
- not support this (very unlikely - at least all DEC bridges
- are ok and I believe that was standard de-facto. -ink), we
- must allow for at least one unit. */
- if (ranges->io_end == ranges->io_start)
- ranges->io_end += 1;
- if (ranges->mem_end == ranges->mem_start)
- ranges->mem_end += 1;
-#endif
ranges->io_end = ROUND_UP(ranges->io_end, 4*1024);
ranges->mem_end = ROUND_UP(ranges->mem_end, 1024*1024);
@@ -142,8 +130,11 @@ pci_setup_bridge(struct pci_bus *bus)
l |= ranges.io_end & 0xf000;
pci_write_config_dword(bridge, PCI_IO_BASE, l);
- /* Clear upper 16 bits of I/O base/limit. */
- pci_write_config_dword(bridge, PCI_IO_BASE_UPPER16, 0);
+ /* Set up upper 16 bits of I/O base/limit. */
+ pci_write_config_word(bridge, PCI_IO_BASE_UPPER16,
+ ranges.io_start >> 16);
+ pci_write_config_word(bridge, PCI_IO_LIMIT_UPPER16,
+ ranges.io_end >> 16);
/* Clear out the upper 32 bits of PREF base/limit. */
pci_write_config_dword(bridge, PCI_PREF_BASE_UPPER32, 0);
@@ -155,32 +146,8 @@ pci_setup_bridge(struct pci_bus *bus)
l |= ranges.mem_end & 0xfff00000;
pci_write_config_dword(bridge, PCI_MEMORY_BASE, l);
- /* Set up PREF base/limit. */
- if (bus->resource[2]->start == bus->resource[2]->end) {
- /*
- ** 5.3.2 Prefetchable Memory Base and Limit Address Registers
- ** (From DEC 21154 Data sheet, page 67)
- ** "To turn off the prefetchable memory address range,
- ** write the prefetchable memory base address register
- ** with a value greater than that of the prefetchable
- ** memory limit address register...."
- **
- ** We can't otherwise disable Prefetchable mem window
- ** since the PCI_COMMAND_MEMORY bit is shared with
- ** non-prefetchable MEM window register.
- */
- l = 0x0000ffff;
- } else {
- l = (bus->resource[2]->start >> 16) & 0xfff0;
- l |= bus->resource[2]->end & 0xfff00000;
- }
- pci_write_config_dword(bridge, PCI_PREF_MEMORY_BASE, l);
-
- /* If all devices on the bus and the bridge itself support FBB,
- enable it. pci_enable_device() will enable FBB for devices. */
- pci_read_config_word(bridge, PCI_SEC_STATUS, (u16 *)&l);
- if (!(l & PCI_BRIDGE_CTL_FAST_BACK))
- bus->bridge_ctl &= ~PCI_BRIDGE_CTL_FAST_BACK;
+ /* Disable PREF memory range. */
+ pci_write_config_dword(bridge, PCI_PREF_MEMORY_BASE, 0x0000fff0);
pci_write_config_word(bridge, PCI_BRIDGE_CONTROL, bus->bridge_ctl);
@@ -188,7 +155,6 @@ pci_setup_bridge(struct pci_bus *bus)
pci_set_master(bridge);
}
-
/* Check whether the bridge supports I/O forwarding.
If not, its I/O base/limit register must be
read-only and read as 0. */
@@ -230,9 +196,9 @@ pbus_assign_resources(struct pci_bus *bu
int i;
/* Link bus resources to the bridge ones. */
- for(i=0; i<3; i++) {
+ for (i = 0; i < 3; i++) {
b->resource[i] =
- &bridge->resource[PCI_BRIDGE_RESOURCES+i];
+ &bridge->resource[PCI_BRIDGE_RESOURCES + i];
b->resource[i]->name = bus->name;
}
b->resource[0]->flags |= pci_bridge_check_io(bridge);
@@ -247,7 +213,12 @@ pbus_assign_resources(struct pci_bus *bu
pbus_assign_resources(b, ranges);
- /* Adjust bus limits. */
+ /* PCI-to-PCI Bridge Architecture Specification rev. 1.1 (1998)
+ requires that if there is no I/O ports or memory behind the
+ bridge, corresponding range must be turned off by writing
+ base value greater than limit to the bridge's base/limit
+ registers.
+ This is done automatically for empty (start==end) ranges. */
b->resource[0]->end = ranges->io_end - 1;
b->resource[1]->end = ranges->mem_end - 1;
@@ -280,6 +251,5 @@ pci_assign_unassigned_resources(void)
ranges.mem_end = ranges.mem_start;
ranges.found_vga = 0;
pbus_assign_resources(b, &ranges);
- pcibios_setup_host_bridge(b);
}
}
Index: include/linux/pci.h
===================================================================
RCS file: /var/cvs/linux/include/linux/pci.h,v
retrieving revision 1.12
diff -u -p -r1.12 pci.h
--- include/linux/pci.h 2001/11/29 15:50:01 1.12
+++ include/linux/pci.h 2001/12/29 21:23:22
@@ -506,7 +506,6 @@ void pcibios_update_resource(struct pci_
struct resource *, int);
void pcibios_update_irq(struct pci_dev *, int irq);
void pcibios_fixup_pbus_ranges(struct pci_bus *, struct pbus_set_ranges_data *);
-void pcibios_setup_host_bridge(struct pci_bus *);
/* Backward compatibility, don't use in new code! */