grundler

[grundler@puffin.external.hp.com]

Update of /home/cvs/parisc/linux-2.3/arch/parisc/kernel
In directory puffin.external.hp.com:/tmp/cvs-serv19967/arch/parisc/kernel

Modified Files:
	iosapic.c 
Log Message:


Problem: iosapic not generating interrupts despite eepro100.c card asserting
   PCI INTA line. (Saw this with a PCI analyzer)
Solution: Encoding of the data written Sapic's IRdT is *different* for
   Astro based platforms than for N-class!

WARNING: this is an INTERMEDIATE version. It generates iosapic interrupts
but didn't call the "right" action handler. It might work now or it might
crash. I've built but not tested this version. I'm checking it in to make
sure work to date doesn't get lost.

FIXME:
1) Have hardcoded the txn_addr value for C3k (and probably J5k) for now.
   Need to establish interface between txn_alloc_addr() such that iosapic.c
   code works for Astro-based, N-class, and IA64 machines. All three use
   a different encoding scheme for the "id_eid" field in the IRdT.

2) txn_alloc_irq() needs to accept at least the number of bits wide the
   txn_alloc_data() can return.

Other FIXMEs:
   o mask/unmask: at present, don't need this. Long term: should be handled
     at the CPU level where it's the easiest/fastest. Not every level in the
     call path.
   o use __GFP_WAIT flag for kmallocs?
   o enforce 32-byte alignment for PDC return data
   o Move processor IRQ allocation to the "enable_irq" code path.